(1) Field of the Invention
This invention relates to semiconductor integrated circuit devices, and more particularly to a method for making capacitors under bit lines (CUBS) embedded dynamic random access memory (DRAM). The process is particularly useful for integrating (embedding) high-density memory with logic circuits on the same chip. Polysilicon landing plugs are used in the DRAM for the capacitor node contacts and for the bit line contacts to minimize the capacitor node leakage current. The capacitor-under-bit line (CUB) DRAM allows metal contacts with lower aspect ratio to be made to the logic circuits for lower resistance (RC) contacts and increased circuit performance.
(2) Description of the Prior Art
Capacitor-under-bit line (CUB) are more desirable than capacitor-over-bit line (COB) for embedding DRAM circuits with logic circuits because the contact to the logic circuits can be made with lower aspect ratios. However, one problem in making capacitor-under-bit line (CUB) DRAM is the need to pattern the top polysilicon electrode (plate) for the DRAM capacitor while providing reliable contact openings for bit line contacts between the closely spaced capacitors. This problem is best understood with reference to the schematic cross-sectional view a conventional CUB DRAM shown in FIG. 13 making electrical contact to the N doped region 17 in the substrate 10. Typically the DRAM cell areas are defined on the surface of a silicon substrate 10 by forming a field isolation 12, such as shallow trench isolation (STI), that surrounds and electrically isolates the individual memory cell device areas. A gate oxide 14 is grown on the device areas and a first polysilicon layer 16 with an upper silicide layer 18 is deposited and patterned to form the FET polycide gate electrodes over the device areas and DRAM word lines over the STI 12. A first etch-stop layer 22 (e.g., silicon nitride), a planar insulating layer 24 (comonly referred to as an interlevel dielectric or ILD layer), and a second etch-stop layer 26 are formed sequentially over the polycide gate electrodes. Contact openings 2 and 4 are etched in layers 26, 24 and 22 for the capacitor node contacts and bit line contacts, respectively. A conductively doped second polysilicon layer is deposited and etched or polished back to form polysilicon plugs 30 in the contact apenings 2 and 4. Next, a third polysilicon layer is used to form bottom electrodes 32 by various means, such as the crown shaped capacitors shown in FIG. 13. A thin interelectrode dielectric 34 (not explicitly shown in FIG. 13) is formed on the surface of electrode 32, and a doped conformal fourth polysilicon layer 36 is deposited to form the capacitor top electrodes. The top electrodes 36 then patterned using a photoresist mask 38. Unfortunately, as feature sizes are reduced for increased circuit density, it is also necessary to increase the capacitor height H (greater than 1.0 micrometers) to maintain a reasonable capacitance for storing charge. Therefore, the conventional photoresist mask 38 must be made sufficiently thick to protect the top portion of the capacitor electrodes when plasma etching is used to pattern the fourth polysilicon layer 36. Because of the rough surface topography, the conventional photoresist layer is quite thick. This thick photoresist and the shallow depth of focus required for exposing high resolution images in the photoresist make it difficult to achieve the necessary resolution. This high resolution photoresist patterning and etching is a particular problem for the high aspect ratio openings 6 between the closely spaced capacitors in which polysilicon layer 36 must be etched over the bit line contact opening 4 for the common bit line contact between the adjacent memory cells. Also, the conventional method requires very accurate lithography alignment.
Several methods for making improved DRAM circuits have been reported in the literature. One method for making capacitor-under-bit line (CUB) DRAMs is described in U.S. Pat. No. 5,893,734 to Jeng et al. in which tungsten landing plugs are used to improve the electrical conductivity. In U.S. Pat. No. 5,897,350, Lee et al. teach a method for making a capacitor-over-bit line (COB) DRAM which circumvents the rough topography problem associated with making CUB DRAM structures. In U.S. Pat. No. 5,238,700 to Dennison et al. a method is described for making a CUB structure in which contact openings are etched through an insulating layer and through the capacitor polysilicon top electrode to the bit line landing plug. The polysilicon top electrode exposed in the bit line contact opening is then recessed and oxidized before the bit line contact is formed in the contact opening. Other methods for making DRAM capacitors are described in U.S. Pat. No. 5,902,126 to Hong et al. in which the capacitor is made over the bit line (COB), and in U.S. Pat. No. 5,888,863 to Tseng a method for fabricating capacitors in memory circuits in described, but do not address the bit line contacts. In U.S. Pat. No. 5,895,250 to Wu a method is described for making semicrown shaped capacitors, but the method for making bit line contacts is also not addressed.
However, there is still a need in the semiconductor industry to provide a very cost-effective process for making capacitor-under-bit lines embedded DRAM circuits that minimize the contact aspect ratio for logic circuits while increasing memory cell density and minimizing capacitance node leakage current.
It is a principal object of the present invention to make capacitors under bit lines (CUB) embedded DRAM circuits with high performance logic circuits on the same chip that result in reduced aspect ratio contacts.
It is another object of the present invention to achieve the above objective using polysilicon plug contacts in the DRAM cells to minimize the capacitor node leakage currents while reducing the aspect ratio for the contacts to the logic circuits.
It is still another object of this invention, by a first embodiment, to use a bottom antireflecting coating (BARC) to fill the narrow spaces between adjacent stacked capacitors. This reduces the rough topography over the capacitors and allows an overlying photoresist layer to be exposed and developed with better definition (fidelity) for patterning the capacitor top electrodes. This provides more reliable contact openings to the bit line polysilicon land plug contacts.
Still another object of this invention, by a second embodiment, is to use a plasma enhanced chemical vapor deposition (PECVD) to deposit a non-conformal silicon oxide (SiOX) layer having a thicker portion on the top of the capacitors and a thinner portion at the base between the closely spaced capacitors. The PECVD oxide layer is anisotropically plasma etched back to form self-aligned openings between the capacitors. The PECVD oxide mask with these self-aligned openings is then used to etch open areas in the capacitor polysilicon top electrodes aligned over the polysilicon landing plugs for the bit line contacts.
Another object of the invention is to provide a process which is compatible with forming a hemispherical silicon grain (HSG) surface on the polysilicon bottom electrode of the capacitor to increase the capacitance.
The method for making these improved embedded DRAM logic circuits starts by providing a semiconductor substrate. Typically the substrate is a Pxe2x88x92 doped single-crystal silicon having a  less than 100 greater than  crystallographic orientation. A field oxide is formed using shallow trench isolation (STI) to surround and electrically isolate device areas in logic regions and DRAM regions on the substrate. A thin gate oxide is formed on the device areas. A conductively doped first polysilicon layer is deposited on the substrate and a silicide layer is deposited and patterned to form field effect transistor (FET) polycide gate electrodes on the device areas, and word lines over the STI regions. Source/drain areas are formed by ion implanting an N-type conductive dopant adjacent to the gate electrodes for N-channel FETs. By including a photoresist implant block-out mask, the FET electrical characteristics can be separately modified for both the DRAM and logic circuits, and can include P-channel FETs for fabricating CMOS circuits on the same chip. A conformal insulating layer is deposited and anisotropically etched back to form sidewall spacers on the gate electrodes. Continuing, a first etch-stop layer, for example composed of silicon nitride (Si3N4), is deposited, and a planar first insulating layer, commonly referred to as an interpolysilicon oxide (IPO-1), is formed. Typically the IPO-1 is a chemical vapor deposited (CVD) silicon oxide (SiO2) and is planarized using an etch-back or chemical-mechanical polishing (CMP) technique. Contact openings are etched in the first insulating layer and the first etch-stop layer to the source/drain areas in the memory regions for capacitor node contacts and bit line contacts. A polysilicon layer is deposited with an N-type dopant and polished back to form polysilicon plugs in the contact openings. A second etch-stop layer, such as Si3N4, is deposited on the planar first insulating layer and a second insulating layer, such as a CVD SiO2, is deposited. Next, capacitor openings are etched in the second insulating layer and the second etch-stop layer aligned over and etched to the polysilicon plugs in the capacitor node contact openings, in which the array of storage capacitors are formed for the embedded DRAM circuits. An N-type doped conformal third polysilicon layer is deposited and polished back to the second insulating layer to form the capacitor bottom electrodes in the capacitor openings. The third polysilicon layer can also be formed as a hemispherical silicon grain layer to increase the surface area and therefore the capacitance. The second insulating layer is then removed selectively to the etch-stop layer using a hydrofluoric acid solution, leaving freestanding crown-shaped capacitor bottom electrodes. A thin interelectrode dielectric layer, such as a silicon oxide/silicon nitride/silicon oxide (ONO), is formed on the bottom electrodes.
Relating now more specifically to the invention, an N doped blanket conformal fourth polysilicon is deposited, sufficiently thick to fill the openings in the crown-shaped capacitor bottom electrodes while forming a conformal layer between adjacent capacitor bottom electrodes. Now a key feature of the invention is to avoid the rough topography problem, cited in the prior art of FIG. 13, by depositing a bottom antireflecting coating (BARC) sufficiently thick to essentially fill the spaces between the capacitors. A photoresist layer is then coated on the substrate having an improved profile over the space between capacitors. This improved photoresist profile results in optical exposure of the photoresist with improved resolution (fidelity) needed because of the shallower depth of focus (DOF) required to form submicrometer images. After the photoresist image is developed, the bottom antireflective coating (BARC) is then anisotopically plasma etched to form well defined openings between the capacitors and over the bit line contacts. The patterned photoresist/BARC etch mask and anisotropic plasma etching are used to pattern the fourth polysilicon layer to form capacitor top electrodes, and concurrently to expose the second etch-stop layer over the polysilicon plugs in the bit line contact openings. The embedded DRAM and logic are now completed to the first level of metal interconnections by depositing a fourth insulating layer over the capacitors. This layer, commonly referred to as an interlevel dielectric (ILD) layer, is typically a CVD SiO2, and is chemical-mechanical polished back to provide a planar surface for the next level of interconnections. Via holes are etched in the fourth insulating layer to the polysilicon plugs in the bit line contact openings, to the capacitor top electrodes, and concurrently etched to the source/drain contact areas and the FET gate electrodes in the logic regions. Since the CUB embedded DRAMs do not include the additional polysilicon and insulating layers necessary for making COB DRAMs, the via holes are substantially reduced in aspect ratio. Metal plugs are now formed in the via holes by depositing a tungsten metal and etching or polishing back to the surface of the fourth insulator. A metal layer, such as an aluminum-copper (Al/Cu) alloy is deposited and patterned to form bit lines for the embedded DRAM circuits and for the first level of metal interconnections for the logic.
In a second embodiment, the process is the same as the first embodiment up to and including the deposition of the fourth polysilicon layer for the capacitor top electrodes (plates). However, in this embodiment the BARC is not used. Instead, a plasma enhanced CVD (PECVD) silicon oxide (SiO2) layer is deposited which is thicker on the top surface of the capacitors than in the spaces between the capacitors. The CVD) oxide is then blanket anisotropically plasma etched back to form openings in the thin CVD) oxide between the capacitors while portions of the thicker oxide remain on the top and sides of the capacitors to protect the capacitor from etching. This results in self-aligned openings over the bit line contacts openings between the capacitors. A photoresist mask and plasma etching are then used to pattern the fourth polysilicon layer to complete the capacitor top electrodes. The remaining process steps for the second embodiment are then completed to the first level of interconnections as described in the first embodiment.